Plan views of the structures of two gallium arsenide (GaAs) FETs which have been widely used are shown in FIGS. 3(a) and 3(b). Each of the FETs shown is formed on a semiconductor substrate 1, usually GaAs. This discrete semiconductor substrate carrying one or more FETs is referred to here as a chip. Each of the chips 100 of FIGS. 3(a) and 3(b) includes one FET. Source electrodes 2, gate electrodes 3, and drain electrodes 4 are disposed on a surface of the GaAs substrate 1. The source and drain electrodes 2 and 4 are electrically connected to the source and drain, respectively, of the FET. The source and drain are formed in the semiconductor substrate 1 in a conducting layer disposed at the surface of the semiconductor substrate 1. The electrically conducting layer may be formed by any conventional process, such as ion implantation, diffusion, or the like. A thin linear gate 3a is located between the source and drain of each transistor and is connected to the gate electrode 3.
In the structure of FIG. 3(a), the length of linear gate 3a lies at a right angle to the flow of the signal which is input to the gate electrode 3 and output from the drain electrode 4. In the structure of FIG. 3(b), four linear gates 3a lie parallel to the signal flow from the gate electrode 3a to the drain electrode 4.
FIG. 4 shows the FET chip 100 of FIG. 3(a) connected in a microstrip transmission line 20. Transmission line 20 includes linear, relatively narrow conductors 7 and 8 disposed on respective dielectric substrates 9 and 10. The source electrode from FET chip 100 is connected to ground by a wire 12. Transmission line 20 may include a ground plane disposed on the opposite side of the dielectric substrates 9 and 10 from conductors 7 and 8 to which wire 12 is connected. The gate electrode 3 and the drain electrode 4 of the chip 100 are connected to microstrip conductors 7 and 8 by wires 13 and 14, respectively. Wires 12, 13, and 14 may be relatively thin gold wires. A direct current (DC) bias voltage is applied to the gate electrode 3 and the drain electrode 4 through the microstrip transmission line conductors 7 and 8. The microwave signal to be amplified is supplied through the microstrip conductor 7 and the wires 13 to the gate electrode 3. The amplified signal is output to microstrip transmission line conductor 8 through the drain electrode 4 in the wires 14.
The characteristics of assemblies of FET chips 100 connected in microstrip transmission line mountings can vary a great deal from assembly to assembly. These performance variations can result from variations in the lengths and positions of the connection wires 12, 13, and 14, since those wires are subject to bending and variations in their relative bonding positions on the respective electrodes when chips are mounted in transmission lines. These variations alter the values of the parasitic reactive circuit elements that are always present in the assembly, particularly the parasitic inductance. The parasitic elements limit the gain, frequency, response, and other performance characteristics of the assembly.
In monolithic FETs, electrodes are directly connected to other circuit elements. An example of a monolithic FET employing an air bridge gate connection is described by Bastida et al in IEEE Transactions on Electron Devices, Volume ED-32, December 1985, pages 2754-2759. In FIGS. 1b and 6 of that article, an FET structure is shown including a gold gate connection from the gate to a gate electrode. The gold connection is spaced by an air gap from an underlying source electrode. The source is grounded through a metal via that passes through the semiconductor substrate from the front side source electrode to a rear side source contact. In one embodiment of the structure disclosed, the air bridge connection to the gate includes a plurality of conducting fingers in a comb-like portion of the air bridge structure. While the air bridge electrode arrangement provides improved amplifier frequency response because of a reduction of the effects of the parasitic elements, the structure disclosed is not suitable for mounting in a microstrip transmission line. Instead, the disclosed structure is connected directly to other amplifier elements on the same substrate employing conventional metal integrated circuit interconnections.
Accordingly, it would be desirable to provide an FET structure suitable for connection in a microstrip transmission line that would be free from variations in the values of parasitic elements from transistor assembly to transistor assembly.